networking – Site Title

Master/Slave controller IP Processor

Digital Blocks offers complete I2C IP Verilog Cores protocol & timing compliant with Master / Slave, Master-only and Slave-only functions. The I2C interface can hold the I2C bus by holding the sclk line low until the host provides more data to enable the transfer to proceed, or until the host allows termination of the transfer.…

March 30, 2020
Display Controller and DMA Controller

Digital Blocks market planning & architecture phases to integrate the system level view of how the IP core functions based on so many years of system level design. We provide our potential customers with pre-verified Verilog / VHDL soft IP cores with System-Level Architecture features which reduce costs and enhance their System’s capabilities and accelerate the…

February 27, 2020

Tag: networking